In recent years, embedded microprocessor has been rapidly used in ours daily life. With the boost of semiconductor technology and the development of architecture technology, new applications need more and more high.performance embedded microprocessors.One way to reach high performance of an embedded microprocessor is downing the technologies used in high-end microprocessors. This leads the mature technologies can be used in embedded microprocessor directly, and improve the embedded microprocessor's performance.Vector technology has been used in many high-end general microprocessors, and gets good result in many applications, such as multimedia applications. Use vector technology in embedded microprocessor should improve its performance in handling multimedia applications, and enlarge the embedded microprocessor's usage:This paper presents an architecture based on the mix-execution of scalar and vector instructions. This architecture has been compared to scalar execution architecture and vector execution architecture. Through the analysis of Petri Net models and the experimental data gained from EDA tools, it is proved that the mix-execution of scalar and vector instructions' architecture is suitable for embedded microprocessor.This paper presents the YH TS-1 instruction architecture, which based on the vector expansion of ARM V4 instruction architecture. It supports vector processing and scalar processing in the same instruction set.This paper also presents a vectorize technology based on the analysis of binary code. It can effective detect the signal loops in the binary code and vectorize the vectorable parts.A 32-bit high performance embedded vector microprocessor architecture YH TS-1 has also been given. It is a RISC microprocessor, has a six-stage pipeline, with separated Data Cache and Instruction Cache.Based on the mix-execution model, the paper discussed the implementation of vector processing in YH TS-1. It supports base vector operations, and it is combined to scalar processing totally.Some key technologies, include the open WISHBONE SoC interface and low power design technology in YH TS-1, have been researched deeply.The full schemes of FPGA and ASIC implementation of YH TS-1 have been given at the end of this paper. YH TS-1 has been verified on FPGA, and the ASIC implementation based on UMC 0.25um process will be completed soon.YH TS-1 is a high performance embedded vector microprocessor, it is compatible to mainstream embedd microprocessor, it support vector processing and has friendly interface. YH TS-1 is a fully intellectual property high performance embedded vector microprocessor.